Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 609 of 698
REJ09B0074-0700
Program-halted state
Program execution state
Reset execution state
SCK2 to
SCK0 = 0
SCK2 to
SCK0 ≠ 0
SLEEP instruction
Any interrupt
SLEEP instruction
Interrupt *
1
SLEEP instruction
SLEEP instruction
Interrupt *
2
Interrupt *
1
,
LSON bit = 1
STBY pin = High
RES pin = Low
STBY pin = Low
SSBY = 0, LSON = 0
SSBY = 1,
PSS = 0, LSON = 0
RES pin = HighMRES pin = High
: Transition after exception processing
Notes:
1. NMI and IRQ0 to IRQ4, IRQ7, RTC interrupt, and USB suspend/resume interrupt
2. NMI and IRQ0 to IRQ4, IRQ7, RTC interrupt, and WDT interrupt
: Power-down
Power-on
reset state
Manual
reset state
High-speed mode
(main clock)
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
SSBY = 1,
PSS = 1, DTON = 0
SSBY = 0,
PSS = 1, LSON = 1
Sub-speed mode
(subclock)
Watch mode
(subclock)
Medium-speed
mode
(main clock)
SLEEP Instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
After the oscillation
settling time (STS2 to 0),
clock switching exception
processing
SLEEP Instruction
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
Clock switching
exception processing
Sub-active
mode
(sub clock)
SLEEP instruction
Interrupt *
1
,
LSON bit = 0
When a transition is made between modes by means of an interrupt, the transition cannot be
made on interrupt source generation alone. Ensure that interrupt handling is performed after
accepting the interrupt request.
From any state except hardware standby mode, a transition to the power-on reset state occurs
when RES is driven low. From any state except hardware standby mode and power-on reset, a
transition to the manual reset state occurs when MRES is driven low.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
Always select high-speed mode before making a transition to watch mode or subactive mode.
Figure 20.1 Mode Transition Diagram