Datasheet

Section 19 Clock Pulse Generator
Rev.7.00 Dec. 24, 2008 Page 602 of 698
REJ09B0074-0700
Table 19.4 External Clock Input Conditions when Duty Adjustment Circuit Is not Used
Item Symbol min max Min max min max Unit
Test
Conditions
External clock input low pulse width t
EXL
80 — 31.25 — 20.8 — ns Figure 19.5
External clock input high pulse width t
EXH
80 — 31.25 — 20.8 — ns
External clock rise time t
EXr
— 15 — 6.25 — 5.25 ns
External clock fall time t
EXf
— 15 — 6.25 — 5.25 ns
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 19.5 External Clock Input Timing
19.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
19.4 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
19.5 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).