Datasheet

Section 19 Clock Pulse Generator
Rev.7.00 Dec. 24, 2008 Page 596 of 698
REJ09B0074-0700
19.1 Register Descriptions
The on-chip clock pulse generator has the following registers.
• System clock control register (SCKCR)
• Low-power control register (LPWRCR)
19.1.1 System Clock Control Register (SCKCR)
SCKCR controls φ clock output and medium-speed mode.
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W φ Clock Output Disable
Controls φ output. The operation of this bit changes
depending on the operating mode. For details, see section
20.11, φ Clock Output Disabling Function.
0: φ output, fixed high, or high impedance
1: Fixed high or high impedance
6 — 0 R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.
5, 4 — All 0 — Reserved
These bits are always read as 0.
3 — 0 R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.