Datasheet

Section 1 Overview
Rev.7.00 Dec. 24, 2008 Page 6 of 698
REJ09B0074-0700
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
VCC VCC VSS VSS DrVCC DrVSS
PA3/SCK2
PA2/RxD2
PA1/TxD2
P36(PUPD+)
P32/SCK0/IRQ
4
P31/RxD0
P30/TxD0
P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD
PG1/IRQ7
PF7/φ
PF3/ADTRG/IRQ3
PF0/IRQ2
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLVSS
OSC1
OSC2
P96/AN14 P97/AN15
Vref
H8S/2000 CPU
WDT
DMAC
USB
P40/AN0 P41/AN1 P42/AN2 P43/AN3
SCI2
STBY
RES
NMI
FWE*
1
USPND/TMOW
USD+
USD-
UBPM
VBUS
ROM
RAM
RTC
NC*
2
P77*
2
P76*
2
P75*
2
NC*
2
PG0*
2
Peripheral data bus
Peripheral address bus
Ports 7 and G*
2
TPU (3 channels)
Interrupts controller
Port E
Port APort 3
Port FPort G
Port 9Port 4
Port 1
Main clock
pulse
generator
Sub-clock
pulse
generator
SCI0 (High speed UART)
A/D converter (6 channels)
Internal address bus
Internal data bus
Bus controller
Notes: NC (no connection): These pins should not be connected; they should be left open.
1. The FWE pin is provided only in the flash memory version. It should be fixed low.
2. The port function is available and the pins function as NC, P77, P76, P75, NC, and PG0, respectively.
Figure 1.4 Internal Block Diagram of HD6432211, HD6432210 and HD6432210S