Datasheet

Section 17 Flash Memory (F-ZTAT Version)
Rev.7.00 Dec. 24, 2008 Page 561 of 698
REJ09B0074-0700
17.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 17.2.
Table 17.2 Pin Configuration
Pin Name I/O Function
RES Input Reset All
FWE Input Flash program/erase protection by hardware
MD2, MD1, MD0 Input Sets this LSI's operating mode
PF3, PF0, P16,
P14
Input Sets this LSI's operating mode in programmer
mode
EMLE Input Emulator enable
TxD2 Output Serial transmit data output
RxD2 Input Serial receive data input
HD64F2218,
HD64F2212,
HD64F2211
USD+, USD− Input/output USB data input/output
VBUS Input USB cable connect/cut detect
UBPM Input USB bus power mode/self power mode select
HD64F2218U,
HD64F2218CU,
HD64F2217CU,
HD64F2212U,
HD64F2212CU,
HD64F2211U
USPND Output USB suspend output
P36 (PUPD+) Output D+ pull-up control
17.5 Register Descriptions
The flash memory has the following registers. For details on register addresses and register states
during each processing, refer to section 21, List of Registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
• RAM emulation register (RAMER)
• Serial control register X ( SCRX)
The masked ROM version is not equipped with the above registers. Attempting to read them with
produce an undetermined value, and writing to them is invalid.