Datasheet

Section 1 Overview
Rev.7.00 Dec. 24, 2008 Page 5 of 698
REJ09B0074-0700
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
VCC VCC VSS VSS DrVCC DrVSS
PA3/SCK2
PA2/RxD2
PA1/TxD2
P36(PUPD+)
P32/SCK0/IRQ
4
P31/RxD0
P30/TxD0
P10/TIOCA0 P11/TIOCB0 P12/TIOCC0/TCLKA P13/TIOCD0/TCLKB P14/TIOCA1/IRQ0 P15/TIOCB1/TCLKC P16/TIOCA2/IRQ1 P17/TIOCB2/TCLKD
PG1/IRQ7
PF7/φ
PF3/ADTRG/IRQ3
PF0/IRQ2
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLVSS
OSC1
OSC2
P96/AN14 P97/AN15
Vref
H8S/2000 CPU
WDT
DMAC
USB
P40/AN0 P41/AN1 P42/AN2 P43/AN3
SCI2
STBY
RES
NMI
FWE
USPND/TMOW
USD+
USD-
UBPM
VBUS
ROM
RAM
RTC
EMLE* TDO/P77* TCK/P76* TMS/P75* TRST/NC*
TDI/PG0*
Note: NC (no connection): This pin should not be connected; it should be left open.
* When EMLE = 0, port function is available and the pins function as P77, P76, P75, NC, and PG0, respectively.
When EMLE = 1, H-UDI function is available and the pins function as TDO, TCK, TMS, TRST, and TDI, respectively.
Peripheral data bus
Peripheral address bus
H-UDI/ports
7 and G*
TPU (3 channels)
Interrupts controller
Port E
Port APort 3
Port FPort G
Port 9Port 4
Port 1
Main clock
pulse
generator
Sub-clock
pulse
generator
SCI0 (High speed UART)
A/D converter (6 channels)
Internal address bus
Internal data bus
Bus controller
Figure 1.3 Internal Block Diagram of HD64F2212, HD64F2212U, HD64F2212CU,
HD64F2211, HD64F2211U, HD64F2211CU and HD64F2210CU