Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 533 of 698
REJ09B0074-0700
14.8.14 Pin Processing when USB Not Used
Pin processing should be performed as follows.
DrVCC = VCC, DrVSS = 0 V, USD+ = USD− = USPND = open state, VBUS = UBPM = 0 V
14.8.15 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP1, or EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 14.30, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAK if the FIFO of the target EP has no data
when receiving the IN token, but the TR interrupt flag is set only after a NAK handshake
is sent. If the next IN token is sent before PKTE of UTRG0 is written to, the TR interrupt
flag is set again.
CPU
Host IN token IN token IN token
Sets TR flag
(Sets the flag again)
Sets TR flag
Determines whether
to return NAK
Transmits data
TR interrupt routine
Clear
TR flag
Writes
transmit data
UTRG0/
PKTE
TR interrupt routine
USB
NAK
Determines whether
to return NAK
NAK
ACK
Figure 14.30 TR Interrupt Flag Set Timing
14.8.16 Clearing the FIFO when DMA Transfer Is Enabled
When DMA transfer is enabled (EP2T1 = 1 and EP2T0 = 0 or 1 in UDMAR) at endpoint 2, it is
not possible to clear OUTFIFO in EP2. It is necessary to disable DMA transfer (EP2T1 = 0 and
EP2T0 = 0 in UDMAR) before clearing the FIFO.