Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 496 of 698
REJ09B0074-0700
Register
Bit
Transfer
Mode
Interrupt
Source
Description
Interrupt
Request
Signal
DMAC
Activation by
USB
Request*
5
UIFR3 0 ⎯
(Status)
VBUSi VBUS interrupt EXIRQ0 or
EXIRQ1
×
1 (VBUSs) VBUS status × ×
2 SPRSi Suspend/resume
interrupt
IRQ6 *
4
×
3 (SPRSs) Suspend/resume
status
× ×
4 Reserved ⎯ ⎯ ⎯
5 SETC Set_Configuration
detection
EXIRQ0 or
EXIRQ1
×
6 SOF Start of Frame packet
detection
EXIRQ0 or
EXIRQ1
×
7 CK48READY USB operating clock
stabilization detection
EXIRQ0 or
EXIRQ1
×
Notes: 1. EP0 interrupts must be assigned to the same interrupt request signal.
2. An EP1 DMA transfer by a USB request is specified by the EP1T1 and EP1T0 bits in
UDMAR.
3. An EP2 DMA transfer by a USB request is specified by the EP2T1 and EP2T0 bits in
UDMAR.
4. The suspend/resume interrupt request IRQ6 must be specified to be detected at the
falling edge (IRQ6SCB and IRQ6SCA in ISCRH = 01) by the interrupt controller register.
5. The DREQ signal is not used for auto-request. The CPU can activate the DMAC using
any flags and interrupts.
• EXIRQ0 signal
The EXIRQ0 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ0 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• EXIRQ1 signal
The EXIRQ1 signal requests interrupt sources for which the corresponding bits in interrupt
select registers 0 to 3 (UISR0 to UISR3) are cleared to 0. The EXIRQ1 is driven low if a
corresponding bit in the interrupt flag register is set to 1.
• IRQ6 signal
The IRQ6 signal is specific to the suspend/resume interrupt request. The falling edge of the
IRQ6 signal is output at the transition from the suspend state or from the resume state.