Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 487 of 698
REJ09B0074-0700
14.3.24 USB Interrupt Select Register 3 (UISR3)
UISR3 sets EXIRQ to output interrupt request indicated in the interrupt flag register 3 (UIFR3).
When a bit in UIER3 corresponding to the UISR3 bit is cleared to 0, an interrupt request is output
from EXIRQ0. When a bit in UIER3 corresponding to the UISR3 bit is set to 1, an interrupt
request is output from EXIRQ1.
Bit Bit Name Initial Value R/W Description
7 CK48READYS 0 R/W Selects the CK48READY interrupt.
6 SOFS 0 R/W Selects the SOF interrupt.
5 SETCS 0 R/W Selects the SETC interrupt.
4 to 1 — All 0 R Reserved
These bits are always read as 0.
0 VBUSiS 0 R/W Selects the VBUSi interrupt.
14.3.25 USB Data Status Register (UDSR)
UDSR indicates whether the IN FIFO data registers (EP1, and EP3) contain valid data or not. A bit
in USDR is set when data written to the corresponding IN FIFO becomes valid after the
corresponding PKTE bit in UTRG is set to 1. A bit in USDR is cleared when all valid data is sent
to the host. For EP1, having a dual-FIFO configuration, the corresponding bit in USDR is cleared
to 0 and FIFO becomes empty.