Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 433 of 698
REJ09B0074-0700
D0 D1D2D3D4 D5D6 D7Dp DE Ds D0D1 D2D3D4 D5D6 D7Dp
(DE)
Ds
D0 D1 D2D3D4Ds
Transfer
frame n + 1
Retransferred framenth transfer frame
TDRE
TEND
FER/ERS
Transfer to TSR from TDR Transfer to TSR from TDR
Transfer to TSR
from TDR
Figure 12.29 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 12.30.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard
time
When GM = 0
When GM = 1
Start bit
Data bits
Parity bit
Error signal
Legend:
Ds:
D0 to D7:
Dp:
DE:
Figure 12.30 TEND Flag Generation Timing in Transmission Operation