Datasheet
Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 393 of 698
REJ09B0074-0700
25 1 2
6 MHz
5.52 MHz
Example for TPU clock generation for 345 kbps average transfer rate when φ = 24 MHz (TCS2 to TCS0 = B'010)
(1) 6-MHz base clock provided by TPU_0 is multiplied by 23/25 by TPU_1 and TPU_2 to generate 5.52-MHz base clock
(2) By making 1 bit = 16 base clocks, the average transfer will be 5.52 MHz/16 = 345 kbps
TPU and SCI settings
Base clock
TIOCA0 (TPU_0) output
= 6 MHz
TIOCA1(TPU_1) output
SCK0
Base clock
= 6 MHz × 23/25
= 5.52 MHz (Average)
1 bit = Base clock × 16*
Average transfer rate = 5.52 MHz/16 = 345 kbps
Note: * The length of one bit varies according to the base clock synchronization.
345678910 212223242511 12 13 14 15 16 17 18 19 20 1 2 3 1234 5 6 7 8 9 10 21 22 23 24 2511 12 13 14 15 16 17 18 19 20
12345678910 21222311 12 13 14 15 16 17 18 19 20 1 2 3 124 5 6 7 8 9 10 21 22 2311 12 13 14 15 16 17 18 19 20
12345678910 56711 12 13 14 15 16 1 2 3 4 8 9 10 15 1611 12 13 14 15 16 1 12 13 142 3 4 5 6 7 8 9 10 11
TIOCA2(TPU_2) output
Clock enable
(TIOCA1×TIOCA2) output
• TCR_0 = H'20 [TCNT_0 cleared by TGRA_0 compare match, TCNT_0 incremented at rising edge of φ/1]
• TCR_1 = H'2D [TCNT_1 cleared by TGRA_1 compare match, TCNT_1 incremented at falling edge of TCLKB]
• TCR_2 = H'2D [TCNT_2 cleared by TGRA_2 compare match, TCNT_2 incremented at falling edge of TCLKB
• TMDR_0 = TMDR_1 = TMDR_2 = H'C2 [PWM mode 1]
• TIORH_0 = H'21 [0 as TIOCA0 initial output, 0 output on TGRA_0 compare match, 1 output on TGRB_0 compare match]
• TIOR_1 = H'21 [0 as TIOCA1 initial output, 0 output on TGRA_1 compare match, 1 output on TGRB_1 compare match]
• TIOR_2 = H'21 [0 as TIOCA2 initial output, 0 output on TGRA_2 compare match, 1 output on TGRB_2 compare match]
• TCNT_0 = TCNT_1 = H'0000, TCNT_2 = H'000C
• TGRA_0 = H'0003, TGRB_0 = H'0001
• TGRA_1 = H'0018, TGRB_1 = H'0000
• TGRA_2 = H'0018, TGRB_2 = H'0000
• SCR_0 = H'03 (external clock)
• SEMRA_0 = H'24 (TCS2 to TCS0 = B'010, ABCS = 0, ACS2 to ACS0 = B'100)
• SEMRB_0 = H'00 (ACS3 = 0)
TPU
TIOCA2
Clock enable
Base clock
φ
TIOCA1
TIOCC0
TIOCA0
TCLKA
TCLKB
SCI_0
SCK0
D
>CK
Q
Figure 12.4 Example of Average Transfer Rate Setting when TPU Clock Is Input (3)