Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 383 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
1 MPB 0 R Multiprocessor Bit
This bit is not used in Smart Card interface mode.
0 MPBT 0 R/W Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Note: 1. The write value should always be 0 to clear the flag.
2. To clear the flag by the CPU on the HD6432210S, reread the flag after writing 0 to it.
12.3.8 Smart Card Mode Register (SCMR)
SCMR is a register that selects the transfer format. In this LSI, Smart Card interface mode cannot
be specified.
Bit Bit Name Initial Value R/W Description
7 to 4 — All 1 — Reserved
These bits are always read as 1.
3 DIR 0 R/W Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data format
is 8 bits.
2 INV 0 R/W Data Invert
Specifies inversion of the data logic level. The SINV bit
does not affect the logic level of the parity bit. To invert
the parity bit, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
data is stored as it is in RDR
1: TDR contents are inverted before being transmitted.
Receive data is stored in inverted form in RDR
1 — 1 — Reserved
This bit is always read as 1.
0 SMIF 0 R/W Smart Card Interface Mode Select
When this bit is set to 1, smart card interface mode is
selected.
0: Normal asynchronous or clocked synchronous mode
1: Smart card interface mode