Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 365 of 698
REJ09B0074-0700
12.1.1 Block Diagram
Figure 12.1 shows the block diagram of the SCI_0. Figure 12.2 shows the block diagram of the
SCI_2.
RxD0
TxD0
PG1/IRQ7
C/A
CKE1
SSE
SCK0
Clock
External clock
TEI
TXI
RXI
ERI
RSR:
RDR:
TSR:
TDR:
SMR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
SCR:
SSR:
SCMR:
BRR:
SEMRA_0:
SEMRB_0:
Serial control register
Serial status register
Smart card mode register
Bit rate register
Serial extended mode register A_0
Serial extended mode register B_0
SCMR
SSR
SCR
SMR
SEMRA_0
SEMRB_0
control
transmission
and reception
Baud rate
generator
Average transfer
rate generator
10.667 MHz
· 115.152 kbps
· 460.606 kbps
16 MHz
· 115.196 kbps
· 460.784 kbps
· 720 kbps
· 921.569 kbps
24 MHz
· 115.132 kbps
· 460.526 kbps
· 720 kbps
· 921.053 kbps
BRR
TPU
TIOCC0
TIOCA1
TIOCA0
TIOCA2
Module data bus
RDR
TSRRSR
Parity generation
Legend:
TDR
SCI transfer
clock generator
in TPU
Parity
check
Internal data bus
Bus interface
φ
φ/4
φ/16
φ/64
Figure 12.1 Block Diagram of SCI_0