Datasheet

Section 10 Watchdog Timer (WDT)
Rev.7.00 Dec. 24, 2008 Page 342 of 698
REJ09B0074-0700
10.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized
to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by
overflows.
Bit Bit Name Initial Value R/W Description
7 WOVF 0 R/(W)*
1
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and the write value should always be 0.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1, and
then writing 0 to WOVF
6 RSTE 0 R/W Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
5 RSTS 0 R/W Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset*
2
1: Manual reset*
3
4 to 0 — All 1 — Reserved
These bits are always read as 1 and cannot be
modified.
Notes: 1. The write value should always be 0 to clear this flag.
2. Bear in mind that the USB register is not initialized by a power-on reset trigged by the
WDT. For details, see section 14.8.8, Reset.
3. Supported only by the H8S/2218 Group.