Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 300 of 698
REJ09B0074-0700
H
L
TCR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 9.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
H
L
TMDR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 9.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
H
L
TCR TMDR
Internal data bus
Bus interface
Module
data bus
Bus
master
Figure 9.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]