Datasheet

Section 9 16-Bit Timer Pulse Unit (TPU)
Rev.7.00 Dec. 24, 2008 Page 280 of 698
REJ09B0074-0700
Table 9.3 CCLR2 to CCLR0 (channel 0)
Bit 7 Bit 6 Bit 5
Channel CCLR2 CCLR1 CCLR0 Description
0 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare
match/input capture
1 0 TCNT cleared by TGRB compare
match/input capture
1 TCNT cleared by counter clearing for
another channel performing synchronous
clearing/synchronous operation*
1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare
match/input capture*
2
1 0 TCNT cleared by TGRD compare
match/input capture*
2
1 TCNT cleared by counter clearing for
another channel performing synchronous
clearing/synchronous operation*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register. TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture dose not occur.
Table 9.4 CCLR2 to CCLR0 (channels 1 and 2)
Bit 7 Bit 6 Bit 5
Channel Reserved*
2
CCLR1 CCLR0 Description
1, 2 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare
match/input capture
1 0 TCNT cleared by TGRB compare
match/input capture
1 TCNT cleared by counter clearing for
another channel performing synchronous
clearing/synchronous operation*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. It is always read as 0 and cannot be modified.