Datasheet

Rev.7.00 Dec. 24, 2008 Page xxiv of liv
REJ09B0074-0700
6.6.2 Valid Strobes ........................................................................................................ 135
6.6.3 Basic Timing ........................................................................................................ 136
6.6.4 Wait Control......................................................................................................... 145
6.7 Burst ROM Interface ......................................................................................................... 147
6.7.1 Basic Timing ........................................................................................................ 147
6.7.2 Wait Control......................................................................................................... 149
6.8 Idle Cycle .......................................................................................................................... 149
6.9 Bus Release ....................................................................................................................... 153
6.9.1 Bus Release Usage Note....................................................................................... 154
6.10 Bus Arbitration.................................................................................................................. 155
6.10.1 Operation.............................................................................................................. 155
6.10.2 Bus Transfer Timing ............................................................................................ 155
6.10.3 External Bus Release Usage Note ........................................................................ 156
6.11 Resets and the Bus Controller ........................................................................................... 156
Section 7 DMA Controller (DMAC).............................................................................. 157
7.1 Features ............................................................................................................................. 157
7.2 Register Configuration ...................................................................................................... 159
7.3 Register Descriptions......................................................................................................... 161
7.3.1 Memory Address Registers (MAR)...................................................................... 161
7.3.2 I/O Address Register (IOAR)............................................................................... 161
7.3.3 Execute Transfer Count Register (ETCR)............................................................ 162
7.3.4 DMA Control Register (DMACR)....................................................................... 163
7.3.5 DMA Band Control Register (DMABCR)........................................................... 169
7.4 Operation........................................................................................................................... 177
7.4.1 Transfer Modes .................................................................................................... 177
7.4.2 Sequential Mode................................................................................................... 178
7.4.3 Idle Mode ............................................................................................................. 181
7.4.4 Repeat Mode ........................................................................................................ 183
7.4.5 Normal Mode ....................................................................................................... 186
7.4.6 Block Transfer Mode............................................................................................ 189
7.4.7 DMAC Activation Sources .................................................................................. 194
7.4.8 Basic DMAC Bus Cycles ..................................................................................... 196
7.4.9 DMAC Bus Cycles (Dual Address Mode) ........................................................... 197
7.4.10 DMAC Multi-Channel Operation......................................................................... 202
7.4.11 Relation between the DMAC and External Bus Requests.................................... 203
7.4.12 NMI Interrupts and DMAC.................................................................................. 203
7.4.13 Forced Termination of DMAC Operation............................................................ 204
7.4.14 Clearing Full Address Mode ................................................................................ 205
7.5 Interrupts ........................................................................................................................... 206
7.6 Usage Notes....................................................................................................................... 207