Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 197 of 698
REJ09B0074-0700
7.4.9 DMAC Bus Cycles (Dual Address Mode)
Short Address Mode: Figure 7.15 shows a transfer example in which TEND* output is enabled
and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external
8-bit, 2-state access space to internal I/O space.
φ
DMA read
RD
HWR
TEND*
LWR
DMA write DMA read DMA write DMA read DMA write
DMA
dead
A
ddress bus
Note: * This LSI does not support TEND output.
Bus release Bus release Bus release Bus releas
e
Last transfer cycle
Figure 7.15 Example of Short Address Mode Transfer
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the
bus is released. While the bus is released one or more bus cycles are inserted by the CPU.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
In repeat mode, when TEND* output is enabled, TEND* output goes low in the transfer cycle in
which the transfer counter reaches 0.
Note: * This LSI does not support TEND output.