Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 192 of 698
REJ09B0074-0700
Start
(DTE = DTME = 1)
MARA = MARA – SAIDE · (–1)
SAID
· 2
DTSZ
· ETCRAH
No
Yes
No
Yes
No
Yes
No
Yes
Clear DTE bit to 0
to end transfer
Acquire bus
ETCRAL = ETCRAL–1
Transfer request?
ETCRAL = H'00
Release bus
BLKDIR = 0
ETCRAL = ETCRAH
ETCRB = ETCRB – 1
ETCRB = H'0000
Read address specified by MARA
MARA = MARA + SAIDE · (–1)
SAID
·
2
DTSZ
Write to address specified by MARB
MARB = MARB + DAIDE · (–1)
DAID
· 2
DTSZ
MARB = MARB – DAIDE · (–1)
DAID
· 2
DTSZ
· ETCRAH
Figure 7.12 Operation Flow in Block Transfer Mode