Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 191 of 698
REJ09B0074-0700
Figure 7.11 illustrates operation in block transfer mode when MARA is designated as a block area.
Address T
B
Address B
B
Transfer
A
ddress T
A
Notes:
Address T
A
= L
A
Address T
B
= L
B
Address B
A
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N–1))
Address B
B
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (M · N–1))
L
A
= Value set in MARA
L
B
= Value set in MARB
N = Value set in ETCRB
M = Value set in ETCRAH and ETCRAL
A
ddress B
A
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Figure 7.11 Operation in Block Transfer Mode (BLKDIR = 1)
ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a
single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.
ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register
for which a block designation has been given by the BLKDIR bit in DMACRA is restored in
accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit
is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to
the CPU. Figure 7.12 shows the operation flow in block transfer mode.