Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 189 of 698
REJ09B0074-0700
7.4.6 Block Transfer Mode
In block transfer mode, transfer is performed with channels A and B used in combination. Block
transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in
DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in
response to a single transfer request, and this is executed the specified number of times. The
transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer
source or the transfer destination can be selected as a block area (an area composed of a number of
bytes or words). Table 7.7 summarizes register functions in block transfer mode.
Table 7.7 Register Functions in Block Transfer Mode
Register Function Initial Setting Operation
23 0
MARA
Source address
register
Start address of
transfer source
Incremented/decremented
every transfer, or fixed
23 0
MARB
Description address
register
Start address of
transfer destination
Incremented/decremented
every transfer, or fixed
0
ETCRAH
7
Holds block size Block size Fixed
0
ETCRAL
7
Block size counter Block size decremented every
transfer; ETCRH value
copied when count reaches
H'00
015
ETCRB
Block transfer
counter
Number of block
transfers
Decremented every block
transfer; transfer ends
when count reaches
H'0000
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be
set separately for MARA and MARB. Whether a block is to be designated for MARA or for
MARB is specified by the BLKDIR bit in DMACRA.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.