Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 184 of 698
REJ09B0074-0700
In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number
of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value
reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is
restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR
restoration operation is as shown below.
MAR = MAR – (–1)
DTID
· 2
DTSZ
· ETCRH
The same value should be set in ETCRH and ETCRL.
In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation,
therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the
CPU. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted
from the transfer after that terminated when the DTE bit was cleared. Figure 7.6 illustrates
operation in repeat mode.
A
ddress T
A
ddress B
Transfer
IOAR
1 byte or word transfer performed in
rewponse to 1 transfer request
Notes:
Address
Address
Where:
T = L
B = L + (–1)
DTID
· (2
DTSZ
· (N–1))
L = Value set in MAR
N = Value set in ETCR
Figure 7.6 Operation in Repeat mode