Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 173 of 698
REJ09B0074-0700
Bit Bit Name Initial Value R/W Description
Data Transfer Acknowledge
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source
selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA
= 1, the internal interrupt source selected by the data
transfer factor setting does not issue an interrupt request
to the CPU.
When DTE = 1 and DTA = 0, the internal interrupt source
selected by the data transfer factor setting is not cleared
when a transfer is performed, and can issue an interrupt
request to the CPU in parallel. In this case, the interrupt
source should be cleared by the CPU transfer.
When DTE = 0, the internal interrupt source selected by
the data transfer factor setting issues an interrupt request
to the CPU regardless of the DTA bit setting.
The state of the DTME bit does not affect the above
operations.
11 DTA1 0 R/W Data transfer acknowledge 1
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
channel 1 data transfer factor setting.
0: Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1: Clearing of selected internal interrupt source at time of
DMA transfer is enabled
10 – 0 R/W Reserved
Although this bit is readable/writable, only 0 should be
written to.
9 DTA0 0 R/W Data Transfer Acknowledge 0
Enables or disables clearing, when DMA transfer is
performed, of the internal interrupt source selected by the
channel 0 data transfer factor setting.
0: Clearing of selected internal interrupt source at time of
DMA transfer is disabled
1: Clearing of selected internal interrupt source at time of
DMA transfer is enabled