Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 172 of 698
REJ09B0074-0700
• Full Address Mode
Bit Bit Name Initial Value R/W Description
15 FAE1 0 R/W Full Address Enable 1
Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used
together as a single channel.
0: Short address mode
1: Full address mode
14 FAE0 0 R/W Full Address Enable 0
Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used
together as a single channel.
0: Short address mode
1: Full address mode
13,12 — All 0 R/W Reserved
Although these bits are readable/writable, only 0 should
be written to.