Datasheet

Section 7 DMA Controller (DMAC)
Rev.7.00 Dec. 24, 2008 Page 160 of 698
REJ09B0074-0700
Table 7.1 Short Address Mode and Full Address Mode (For 1 Channel: Example of
Channel 0)
FAE0 Description
0
MAR0A
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source, etc.
Short address mode specified (channels A and B operate independently)
Specifies transfer source/transfer destination address
Specifies transfer destination/transfer source address
Specifies number of transfers
Specifies transfer size, mode, activation source, etc.
Channel 0AChannel 0B
IOAR0A
ETCR0A
DMACR0A
MAR0B
IOAR0B
ETCR0B
DMACR0B
1
MAR0A
IOAR0A
ETCR0A
DMACR0A
MAR0B
IOAR0B
ETCR0B
DMACR0B
Specifies transfer source address
Specifies transfer destination address
Not used
Not used
Specifies number of transfers
Specifies number of transfers (used in block transfer mode only)
Specifies transfer size, mode, activation source, etc.
Full address mode specified (channels A and B operate combination)
Channel 0