Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 154 of 698
REJ09B0074-0700
Figure 6.25 shows the timing for transition to the bus-released state.
CPU
cycle
Address
Minimum
1 state
T
0
T
1
T
2
HWR, LWR
BREQ
BACK
High impedance
High impedance
AS
CSn
High impedance
High impedance
High impedance
RD
High impedance
Data bus
A
ddress bus
φ
[1] [2] [3] [4] [5]
[1] Low level of BREQ pin is sampled at rise of T
2
state.
[2] BACK pin is driven low at end of CPU read cycle, releasing bus to external bus
master.
[3] BREQ pin state is still sampled in external bus released state.
[4] High level of BREQ pin is sampled.
[5] BACK pin is driven high, ending bus release cycle.
CPU cycle External bus released state
Note : n = 0 to 5
Figure 6.25 Bus-Released State Transition Timing
6.9.1 Bus Release Usage Note
When MSTPCR is set to H'FFFFFF and transmitted to sleep mode, the external bus release does
not function. To activate the external bus release in sleep mode, do not set MSTPCR to H'FFFFFF.