Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 150 of 698
REJ09B0074-0700
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output floating time
Data collision
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Address bus
φ
RD
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
T
2
CS (area A)
CS (area B)
CS (area A)
CS (area B)
Figure 6.22 Example of Idle Cycle Operation (1)