Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 136 of 698
REJ09B0074-0700
6.6.3 Basic Timing
8-Bit 2-State Access Space: Figure 6.10 shows the bus timing for an 8-bit 2-state access space in
the H8S/2218 Group. When an 8-bit access space is accessed, the upper half (D15 to D8) of the
data bus is used.
Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
(16-bit bus
mode)
D15 to D8
Valid
D7 to D0
High impedance
High impedance
Write
High
Note: n = 0 to 5
LWR
(8-bit bus
mode)
Figure 6.10 Bus Timing for 8-Bit 2-State Access Space