Datasheet

Section 6 Bus Controller
Rev.7.00 Dec. 24, 2008 Page 132 of 698
REJ09B0074-0700
Bus cycle
T
1
Unchanged
A
ddress bus*
AS*
RD*
HWR, LWR*
Data bus*
Note: * Supported only by the H8S/2218 Group.
φ
High
High
High
High-impedance state
Figure 6.5 Pin States during On-Chip Memory Access
6.5.2 On-Chip Peripheral Module Access Timing
The on-chip peripheral modules are accessed in two states except on-chip USB and RTC. The data
bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed.
Figure 6.6 shows the access timing for the on-chip peripheral modules. Figure 6.7 shows the pin
states.
T
1
T
2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.6 On-Chip Peripheral Module Access Cycle