Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 106 of 698
REJ09B0074-0700
Yes
Program execution status
Interrupt generated?
NMI
Level 6 interrupt?
Mask level 5
or below?
Level 7 interrupt?
Mask level 6
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Level 1 interrupt?
Mask level 0?
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Hold
pending
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 2