Datasheet

Section 5 Interrupt Controller
Rev.7.00 Dec. 24, 2008 Page 91 of 698
REJ09B0074-0700
Section 5 Interrupt Controller
5.1 Features
• Two interrupt control modes
⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
the system control register (SYSCR).
• Priorities settable with IPR
⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Seven external interrupts (NMI, IRQ7, and IRQ4 to IRQ0)
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ7 and IRQ4 to IRQ0. IRQ6 is an interrupt only for the on-
chip USB. IRQ5 is an interrupt only for the on-chip RTC.
• DMAC control
⎯ DMAC activation is performed by means of interrupts.