Datasheet

Section 4 Exception Handling
Rev.7.00 Dec. 24, 2008 Page 89 of 698
REJ09B0074-0700
4.7 Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
CCR
CCR*
1
PC (16 bits)
SP
EXR
Reserved*
1
CCR
CCR*
1
PC (16 bits)
SP
CCR
PC (24 bits)
SP
EXR
Reserved*
1
CCR
PC (24 bits)
SP
(a) Normal Modes*
2
(b) Advanced Modes
Interrupt control mode 0 Interrupt control mode 2
Interrupt control mode 0 Interrupt control mode 2
Notes: 1.
2.
Ignored on return.
Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling