Datasheet

Section 2 CPU
Rev.7.00 Dec. 24, 2008 Page 65 of 698
REJ09B0074-0700
Exception handling state
Bus-released state
Hardware standby mode
*
2
Software standby mode
Reset state
*
1
Sleep mode
Power-down state
*
3
Program execution state
End of bus request
Bus request
Interrupt request
External interrupt request
RES = High
MRES = High
Request for exception handling
STBY = High, RES = Low
End of bus
request
Bus request
SLEEP instruction,
SSBY = 0
SLEEP instruc
tion,
SSBY = 1
Notes: 1.
2.
3.
From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state except hardware standby mode and power-on reset state, a transition to the manual
reset state occurs whenever MRES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
See section 20, Power-Down Modes.
End of exception
handling
Figure 2.13 State Transitions