Datasheet

Section 2 CPU
Rev.7.00 Dec. 24, 2008 Page 46 of 698
REJ09B0074-0700
Table 2.1 Instruction Classification
Function Instructions Size Types
MOV B/W/L 5
POP*
1
, PUSH*
1
W/L
LDM*
5
, STM*
5
L
Data transfer
MOVFPE*
3
, MOVTPE*
3
B
ADD, SUB, CMP, NEG B/W/L 19
ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/L
Arithmetic
operations
TAS*
4
B
Logic operations AND, OR, XOR, NOT B/W/L 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
B/W/L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
B 14
Branch Bcc*
2
, JMP, BSR, JSR, RTS – 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
– 9
Block data transfer EEPMOV – 1
Total: 65
Legend: B: Byte size
W: Word size
L: Longword size
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. ER7 is used as a stack pointer in STM and LDM instructions. ER7, therefore, should not
be used as a saving (STM) or restoring (LDM) register.