Datasheet

Rev.7.00 Dec. 24, 2008 Page viii of liv
REJ09B0074-0700
Item Page Revision (See Manual for Details)
1.2 Internal Block
Diagram
Figure 1.1 Internal
Block Diagram of
HD64F2218,
HD64F2218U,
HD64F2218CU
and HD642217CU
3 Title and figure amended
VCC VCC VSS VSS DrVCC DrVSS EMLE* TDO* TCK* TMS* TRST* TDI*
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLVSS
OSC1
OSC2
STBY
RES
NMI
FWE
USPND/TMOW
Boundary scan/H-UDI*
2
Interrupts controll
Main clock
pulse
generator
Sub-clock
pulse
generator
Note *1 shown below deleted
Notes: 1. The FWE pin is provided only in the HD64F2218 and
HD64F2218U.
Figure 1.2 Internal
Block Diagram of
HD6432217
4 Note amended
1. The FWE pin is provided only in the flash memory version.
Figure 1.3 Internal
Block Diagram of
HD64F2212,
HD64F2212U,
HD64F2212CU,
HD64F2211,
HD64F2211U,
HD64F2211CU and
HD64F2210CU
5 Title and figure amended
VCC VCC VSS VSS DrVCC DrVSS
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLVSS
OSC1
OSC2
STBY
RES
NMI
FWE
USPND/TMOW
EMLE* TDO/P77* TCK/P76* TMS/P75* TRST/NC*
TDI/PG0*
H-UDI/ports
7 and G*
2
Interrupts co
Main clock
pulse
generator
Sub-clock
pulse
generator
Note *1 shown below deleted
Notes: 1. The FWE pin is provided only in the HD64F2212,
HD64F2212U, HD64F2211 andHD64F2211U.