Datasheet

Section 2 CPU
Rev.7.00 Dec. 24, 2008 Page 35 of 698
REJ09B0074-0700
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
Exception vector 1
Exception vector 2
Exception
vector tabl
e
(Reserved for system use)
Figure 2.1 Exception Vector Table (Normal Mode)
(a) Subroutine Branch (b) Exception Handling
PC
(16 bits)
EXR*
1
Reserved*
1
*
3
CCR
CCR*
3
PC
(16 bits)
SP
SP
Notes: 1.
2.
3.
When EXR is not used, it is not stored on the stack.
SP when EXR is not used.
Ignored when returning.
( SP*
2
)
Figure 2.2 Stack Structure in Normal Mode