Datasheet

Section 1 Overview
Rev.7.00 Dec. 24, 2008 Page 25 of 698
REJ09B0074-0700
Pin No.
Type Symbol
TFP-100G,
TFP-100GV
BP-112,
BP-112V
FP-64E,
FP-64EV,
TNP-64B,
TNP-64BV
I/O Function
Bus control HWR 93 B5 ⎯ Output A strobe signal that writes to
external address space and
indicates that the upper half (D15 to
D8) of the data bus is enabled.
(Supported only by the H8S/2218
Group)
LWR 94 C5 ⎯ Output A strobe signal that writes to
external address space and
indicates that the lower half (D7 to
D0) of the data bus is enabled.
(Supported only by the H8S/2218
Group)
WAIT 95 A4 ⎯ Input Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
(Supported only by the H8S/2218
Group)
TCLKA
TCLKB
TCLKC
TCLKD
4
5
7
9
C2
C1
D2
E4
3
4
6
8
Input TPU external clock input pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
2
3
4
5
B1
D4
C2
C1
1
2
3
4
I/O The TGRA_0 to TGRD_0 input
capture input/output compare
output/PWM output pins
TIOCA1
TIOCB1
6
7
D3
D2
5
6
I/O The TGRA_1 and TGRB_1 input
capture input/output compare
output/PWM output pins
16-bit timer
pulse unit
(TPU)
TIOCA2
TIOCB2
8
9
D1
E4
7
8
I/O The TGRA_2 and TGRB_2 input
capture input/output compare
output/PWM output pins
Realtime
clock (RTC)
TMOW 21 G4 12 Output The divided clock output pin