Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 627 of 698
REJ09B0074-0700
20.10 Direct Transitions
There are three modes, high-speed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and subactive modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
20.10.1 Direct Transitions from High-Speed Mode to Subactive Mode
Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 1, and DTON bit = 1, and TSCR_1 PSS bit = 1 to make a transition to subactive
mode.
20.10.2 Direct Transitions from Subactive Mode to High-Speed Mode
Execute the SLEEP instruction in subactive mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR_1 PSS bit = 1 to make a direct transition to high-
speed mode after the time set in SBYCR STS2 to STS0 has elapsed.
20.11 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 20.4 shows the state of the φ pin in each processing state.
Table 20.4 φ Pin State in Each Processing State
Register Settings
DDR PSTOP
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
Sleep Mode, Subsleep
Mode
Software Standby
Mode, Watch Mode,
Direct Transition
Hardware Standby
Mode
0 × High impedance High impedance High impedance High impedance
1 0 φ output φ output Fixed high High impedance
1 1 Fixed high Fixed high Fixed high High impedance
Legend:
×: Don’t care