Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 625 of 698
REJ09B0074-0700
20.8 Subsleep Mode
20.8.1 Transition to Sleep Mode
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR_1 PSS bit = 1, CPU operation shifts to subsleep mode.
In subsleep mode, the CPU is stopped. Peripheral modules other WDT and RTC are also stopped.
The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the
internal peripheral modules (excluding the A/D converter) and I/O ports are retained.
20.8.2 Exiting Subsleep Mode
Subsleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin, or
IRQ0, to IRQ7), or signals at the RES, MRES*, or STBY pin.
• Exiting Subsleep Mode by Interrupts
When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.
In case of IRQ0, to IRQ7interrupts, subsleep mode is not cancelled if the corresponding enable
bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the
internal peripheral modules, the interrupt enable register has been set to disable the reception of
that interrupt, or is masked by the CPU.
• Exiting Subsleep Mode by RES or MRES* pin
For exiting subsleep mode by the RES or MRES* pin, see section 20.4.2, Clearing Software
Standby Mode.
• Exiting Subsleep Mode by STBY Pin
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Note: * Supported only by the H8S/2218 Group.