Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 623 of 698
REJ09B0074-0700
Timing of Recovery from Hardware Standby Mode:
Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a
power-on reset.
t
OSC
t
NMIRH
t ≥100 ns
STBY
RES
NMI
Figure 20.7 Timing of Recovery from Hardware Standby Mode
20.6 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the A/D converter are retained.
After reset clearance, all modules other than DMAC and flash memory are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
When a transition is made to sleep mode with all modules stopped, the bus controller and I/O ports
also stop operating, enabling current dissipation to be further reduced.