Datasheet

Section 20 Power-Down Modes
Rev.7.00 Dec. 24, 2008 Page 617 of 698
REJ09B0074-0700
20.1.4 Extended Module Stop Register (EXMDLSTP)
EXMDLSTP controls the clock supply of the RTC and USB, performs module stop mode control.
Setting a bit to 1, causes the corresponding module to enter module stop mode, while clearing the
bit to 0 clears the module stop mode.
Bit Bit Name Initial Value R/W Module
7 to
2
⎯ Undefined ⎯ Reserved
Read is undefined. These bits should not to be
modified.
1 RTCSTOP 0 R/W RTC
0 USBSTOP1 0 R/W USB
20.2 Medium-Speed Mode
When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus
masters other than the CPU (DMAC) also operate in medium-speed mode. On-chip supporting
modules other than the bus masters always operate on the high-speed clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR, the LSON bit in LPWRCR are
cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt,
medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit = 1 and the LSON bit, and the PSS bit
in TCSR_1 are cleared to 0, operation shifts to the software standby mode. When software standby
mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES or MRES* pin is set low and medium-speed mode is cancelled, operation shifts to
the reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.