Datasheet

Section 19 Clock Pulse Generator
Rev.7.00 Dec. 24, 2008 Page 604 of 698
REJ09B0074-0700
19.7 Subclock Waveform Generation Circuit
To eliminate noise from the subclock input to OSCI, the subclock is sampled using the dividing
clock φ. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see section
19.1.2, Low Power Control Register (LPWRCR).
No sampling is performed in subactive mode, subsleep mode, or watch mode.
19.8 PLL Circuit for USB
The PLL circuit has the function of doubling or tripling the 16-MHz or 24-MHz clock from the
main oscillator to generate the 48-MHz USB operating clock.
When the PLL circuit is used, set the UCKS3 to UCKS0 bits of UCTLR. For details, refer to
section 14, Universal Serial Bus (USB).
When the PLL circuit is not used, connect the PLVCC pin to Vcc and the PLLVSS pin to the
ground (Vss). Figure 19.9 shows examples of external circuits peripheral to the PLL.
16-MHz or
24-MHz
crystal
resonator
or external
clock
(2) PLL is not used(1) PLL is used
Note: * CB, CPB is laminated ceramic.
R
P
: 200Ω
PLLVCC
EXTAL
XTAL
PLLVSS
VCC
VSS
Vcc
CPB: 0.1μF*
CB: 0.1μF*
6- to 24-MHz
crystal
resonator
or external
clock
PLLVCC
EXTAL
XTAL
PLLVSS
VCC
VSS
Vcc
Figure 19.9 Example of PLL Circuit