Datasheet

Section 19 Clock Pulse Generator
Rev.7.00 Dec. 24, 2008 Page 601 of 698
REJ09B0074-0700
19.2.2 Inputting External Clock
An external clock signal can be input as shown in an example in figure 19.4. If the XTAL pin is
left open, make sure that stray capacitance is no more than 10 pF. When complementary clock
input to XTAL pin, the external clock input should be fixed high in standby mode, subactive
mode, subsleep mode, or watch mode.
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
(a) XTAL pin left open
(b) Complementary clock input at XTAL pin
Figure 19.4 External Clock Input (Examples)
Table 19.3 shows the input conditions for the external clock.
Table 19.3 External Clock Input Conditions
VCC= 2.4 to 3.6V VCC = 2.7 to 3.6V VCC = 3.0 to 3.6V
Item Symbol min max Min max min max Unit
Test
Conditions
External clock input low pulse width t
EXL
65 — 25 — 15.5 — ns
External clock input high pulse width t
EXH
65 — 25 — 15.5 — ns
External clock rise time t
EXr
— 15 — 6.25 — 5.25 ns
External clock fall time t
EXf
— 15 — 6.25 — 5.25 ns
Figure 19.5
Clock low pulse width level t
CL
0.35 0.65 0.4 0.6 0.4 0.6 tcyc Figure 22.3
Clock high pulse width level t
CH
0.35 0.65 0.4 0.6 0.4 0.6 tcyc
The external clock input conditions when the duty adjustment circuit is not used are shown in table
19.4. When the duty adjustment circuit is not used, note that the maximum operating frequency
depends on the external clock input waveform. For example, if t
EXL
= t
EXH
= 20.8 ns and t
EXr
= t
EXf
= 5.25 ns, the maximum operating frequency becomes 19.2 MHz depending on the clcok cycle
time of 52.1 ns.