Datasheet

Section 17 Flash Memory (F-ZTAT Version)
Rev.7.00 Dec. 24, 2008 Page 582 of 698
REJ09B0074-0700
Start
Set EBR1 (2)
Enable WDT
Disable WDT
Read verify data
Increment address
Verify data = all 1s?
Last address of block?
All erase block erased?
Set block start address as verify address
H'FF dummy write to verify address
Set SWE1 bit in FLMCR1
n = 1
Set ESU1 bit in FLMCR1
Set E1 bit in FLMCR1
Start erasing
Halt erasing
Wait (x) μs
Wait (y) μs
Clear E1 bit in FLMCR1
Set EV1 bit in FLMCR1
Wait (z) μs
Clear ESU1 bit in FLMCR1
Wait (
α ) μs
Wait (β) μs
Wait (γ) μs
Clear EV1 bit in FLMCR1
n ← n + 1
Wait (η) μs
Clear SWE1 bit in FLMCR1
Wait (θ) μs
Clear EV1 bit in FLMCR1
n ≥ (N)?
Wait (η) μs
Clear SWE1 bit in FLMCR1
Wait (θ) μs
Erase failure
End of erasing
Wait (ε) μs
No
Yes
Yes
No
No
No
Yes
Yes
*1
*2
*2
*2
*2
*2
*2
*2
*2
*5
*2
*3
*4
Notes: 1.
2.
3.
4.
5.
Pre-write (clearing data in the block to be erased to 0) isn not required.
x, y, z, α, β, γ, ε, η, θ, and N are shown in section 22.7, Flash Memory Characteristics.
Veryfy data is read in 16 bits.
Only 1 bit in the EBR register must be set. Two or more bits in EBR cannot be set.
Erasure is performed in block units. To erase multiple blocks, each block must be erased sequentially.
Figure 17.14 Erase/Erase-Verify Flowchart