Datasheet

Section 15 A/D Converter
Rev.7.00 Dec. 24, 2008 Page 545 of 698
REJ09B0074-0700
Table 15.3 A/D Conversion Time (Single Mode)
CKS1 = 0 CKS1 = 1
CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1
Item
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
A/D conversion start
delay
t
D
18 — 33 10 — 17 6 — 9 4 — 5
Input sampling time t
SPL
— 127 — — 63 — — 31 — — 15 —
A/D conversion time t
CONV
515 — 530 259 — 266 131 — 134 67 — 68
Note: All values represent the number of states.
Table 15.4 A/D Conversion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
0 512 (Fixed) 0
1 256 (Fixed)
1 0 128 (Fixed)
1 64 (Fixed)
15.5.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 15.6 shows the
timing.
φ
ADTRG
Internal trigger signal
A
DST
A/D conversion
Figure 15.6 External Trigger Input Timing