Datasheet

Rev.7.00 Dec. 24, 2008 Page li of liv

REJ09B0074-0700

Table 9.3 CCLR2 to CCLR0 (channel 0)............................................................................... 280

Table 9.4 CCLR2 to CCLR0 (channels 1 and 2).................................................................... 280

Table 9.5 TPSC2 to TPSC0 (channel 0)................................................................................. 281

Table 9.6 TPSC2 to TPSC0 (channel 1)................................................................................. 281

Table 9.7 TPSC2 to TPSC0 (channel 2)................................................................................. 282

Table 9.8 MD3 to MD0.......................................................................................................... 283

Table 9.9 TIORH_0 (channel 0)............................................................................................. 285

Table 9.10 TIORH_0 (channel 0)............................................................................................. 286

Table 9.11 TIORL_0 (channel 0) ............................................................................................. 287

Table 9.12 TIORL_0 (channel 0) ............................................................................................. 288

Table 9.13 TIOR_1 (channel 1)................................................................................................ 289

Table 9.14 TIOR_1 (channel 1)................................................................................................ 290

Table 9.15 TIOR_2 (channel 2)................................................................................................ 291

Table 9.16 TIOR_2 (channel 2)................................................................................................ 292

Table 9.17 Register Combinations in Buffer Operation........................................................... 309

Table 9.18 PWM Output Registers and Output Pins................................................................ 314

Table 9.19 Phase Counting Mode Clock Input Pins................................................................. 317

Table 9.20 Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 318

Table 9.21 Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 319

Table 9.22 Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 320

Table 9.23 Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 321

Table 9.24 TPU Interrupts........................................................................................................ 322

Section 10 Watchdog Timer (WDT)

Table 10.1 WDT Interrupt Source............................................................................................ 345

Section 11 Realtime Clock (RTC)

Table 11.1 Pin Configuration ................................................................................................... 350

Table 11.2 Interrupt Source...................................................................................................... 360

Table 11.3 Operating State in Each Mode................................................................................ 362

Section 12 Serial Communication Interface

Table 12.1 Pin Configuration ................................................................................................... 367

Table 12.2 Relationships between the N Setting in BRR and Bit Rate B ................................ 395

Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 396

Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 399

Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 400

Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 401

Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 401

Table 12.8 BRR Settings for Various Bit Rates

(Smart Card Interface Mode, when n = 0 and S = 372).......................................... 402