Datasheet

Section 14 Universal Serial Bus (USB)
Rev.7.00 Dec. 24, 2008 Page 473 of 698
REJ09B0074-0700
14.3.4 USB Trigger Register 0 (UTRG0)
UTRG0 is a one-shot register to generate triggers to the FIFO for each endpoint EP0 to EP3. For
details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit Bit Name Initial Value R/W Description
7, 6 — All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
5 EP2RDFN 0 W EP2 Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP2 OUT
FIFO. EP2 has a dual-FIFO configuration. This
trigger is generated to the currently effective FIFO.
4 EP1PKTE 0 W EP1 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP1 IN FIFO. EP1 has a dual-FIFO configuration.
This trigger is generated to the currently effective
FIFO.
3 EP3PKTE 0 W EP3 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP3 IN FIFO.
2 EP0oRDFN 0 W EP0o Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP0o OUT
FIFO. This trigger enables EP0o to receive the
next packet.
1 EP0iPKTE 0 W EP0i Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP0i IN FIFO.