Datasheet

Section 14 Universal Serial Bus (USB)

Rev.7.00 Dec. 24, 2008 Page 469 of 698

REJ09B0074-0700

Bit Bit Name Initial Value R/W Description

UCKS3

UCKS2

UCKS1

UCKS0

0 R/W USB Operation Clock Select 3 to 0

These bits control the on-chip PLL, which generates

the USB operation clock (48 MHz). When UCKS3 to

UCKS0 are 0000, the PLL circuit stops and thus the

USB operation clock must be selected according to

the clock source.

The on-chip PLL circuit starts operating after the USB

module stop 2 bit has been cancelled. In addition, the

USB operation clock is supplied to the UDC core after

the USB operating clock stabilization time has been

passed. The completion timing of the USB operating

clock stabilization time can be detected by the

CK48READY flag in UIFR3.

UCKS0 to UCKS3 muse be written while the USB

module stop 2 bit (MSTPB0) is 1.

0000: USB operation clock stops (PLL stops)

0001: Reserved

001×: Reserved

010×: Reserved

0110: Uses a clock (48 MHz) generated by doubling

the 24-MHz main oscillation by the PLL.

0111: Uses a clock (48 MHz) generated by tripling the

16-MHz main oscillation by the PLL.

1×××: Reserved

The USB operating clock stabilization time is 2 ms.

Legend:

×: Don't care