Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 396 of 698
REJ09B0074-0700
Timing and Reception Margin. Tables 12.5 and 12.7 show the maximum bit rates with external
clock input.
When the ABCS bit in SCI_0’s serial extended mode register A_0 (SEMRA_0) is set to 1 in
asynchronous mode, the maximum bit rates are twice those shown in table 12.3.
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
2 2.097152 2.4576 3
Bit Rate
(bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%)
110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34
9600 — — — 0 6 –2.48 0 7 0.00 0 9 –2.34
19200 — — — — — — 0 3 0.00 0 4 –2.34
31250 0 1 0.00 — — — — — — 0 2 0.00
38400 — — — — — — 0 1 0.00 — — —