Datasheet

Section 12 Serial Communication Interface
Rev.7.00 Dec. 24, 2008 Page 391 of 698
REJ09B0074-0700
123
4 MHz
3 MHz
Example for TPU clock generation for 187.5 kbps average transfer rate when φ = 16 MHz (TCS2 to TCS0 = B'000)
(1) 4-MHz base clock provided by TPU_1 is multiplied by 3/4 by TPU_2 to generate 3-MHz base clock (2) By making 1 bit = 16 base clocks, the average transfer will be 3 MHz/16 = 187.5 kbps
TPU and SCI settings
B
ase clock
T
IOCA1output
=
4 MHz
C
lock enable
T
IOCA2 output
S
CK0
B
ase clock
=
4 MHz × 3/4
=
3 MHz (Average)
1 bit = Base clock × 16*
Average transfer rate = 3 MHz/16 = 187.5 kbps
Note: * The lengh of one bit varies according to the base clock synchronization.
41234123412 3341234123412
123 123 123 12 33 123 123 12 123 456 789 1011 512 13 14 15 16 1 2 3 4
• TCR_1 = H'20 [TCNT_1 cleared by TGRA_1 compare match, TCNT_1 incremented at rising edge of φ/1] • TCR_2 = H'2C [TCNT_2 cleared by TGRA_2 compare match, TCNT_2 incremented at falling edge of TCLKA • TMDR_1 = TMDR_2 = H'C2 [PWM mode 1] • TIOR_1 = H'21 [0 as TIOCA1 initial output, 0 output on TGRA_1 compare match, 1 output on TGRB_1 compare match] • TIOR_2 = H'21 [0 as TIOCA2 initial output, 0 output on TGRA_2 compare match, 1 output on TGRB_2 compare match] • TCNT_1 = TCNT_2 = H'0000 • TGRA_1 = H'0003, TGRB_1 = H'0001 • TGRA_2 = H'0003, TGRB_2 = H'0001 • SCR_0 = H'03 (external clock) • SEMRA_0 = H'04 (TCS2 to TCS0 = B'000, ABCS = 0, ACS2 to ACS0 = B'100) • SEMRB_0 = H'00 (ACS3 = 0)
Clock enable
Base clock
TPU
TIOCA2 TIOCA1
TIOCC0
TIOCA0
TCLKA TCLKB
SCI_0
SCK0
Figure 12.4 Example of Average Transfer Rate Setting when TPU Clock Is Input (1)